//////////////////////////////////////////////////////////////////////
////                                                              ////
////  LongDelay.v                                                 ////
////                                                              ////
////                                                              ////
////  This file is part of the "Pico E12" project                 ////
////  http://www.picocomputIng.com                                ////
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////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2005, Pico ComputIng, Inc.                     ////
//// http://www.picocomputing.com/                                ////
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//// the origInal copyright notice and the associated disclaimer. ////
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//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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////////////////////////////////////////////////////////////////////JF

`timescale 10ns / 1ns

//This module provides a delay of 35-40 nS on the leading edge and 5-10 nS on the falling edge
//This module should be clocked at 200MHz


module LongDelay(Clock, In, Out);

input Clock;
input In;
output Out;

reg DelayReg[7:0];
wire Out;


always @(posedge Clock) begin
	if (In) begin
   	DelayReg[7] <= DelayReg[6];
		DelayReg[6] <= DelayReg[5];
  	 	DelayReg[5] <= DelayReg[4];
		DelayReg[4] <= DelayReg[3];
   	DelayReg[3] <= DelayReg[2];
		DelayReg[2] <= DelayReg[1];
		DelayReg[1] <= DelayReg[0];
		DelayReg[0] <= In;
	end
else
	begin
		DelayReg[7] <= DelayReg[6];
		DelayReg[6] <= 1'b0;
		DelayReg[5] <= 1'b0;
		DelayReg[4] <= 1'b0;
		DelayReg[3] <= 1'b0;
		DelayReg[2] <= 1'b0;
		DelayReg[1] <= 1'b0;
		DelayReg[0] <= 1'b0;
	end
end

assign Out = DelayReg[7];
	
endmodule